{
  'XILINX' => 'G:/Software/ISE_DS/ISE',
  'clkWrapper' => 'mcodedemo_cw',
  'clkWrapperFile' => 'mcodedemo_cw.v',
  'createTestbench' => 0,
  'design' => 'mcodedemo',
  'designFileList' => [
    'mcodedemo.v',
    'mcodedemo_cw.v',
  ],
  'device' => 'xc6slx9-2tqg144',
  'family' => 'spartan6',
  'files' => [
    'xlpersistentdff.ngc',
    'synopsis',
    'mcodedemo.v',
    'xlpersistentdff.ngc',
    'mcodedemo_cw.v',
    'mcodedemo_cw.ucf',
    'mcodedemo_cw.xcf',
    'mcodedemo_cw.sdc',
    'xst_mcodedemo.prj',
    'xst_mcodedemo.scr',
    'vcom.do',
    'isim_mcodedemo.prj',
  ],
  'hdlKind' => 'verilog',
  'isCombinatorial' => 1,
  'synthesisTool' => 'XST',
  'sysgen' => 'G:/Software/ISE_DS/ISE/sysgen',
  'systemClockPeriod' => 10,
  'testbench' => 0,
  'using71Netlister' => 1,
  'vsimtime' => '110275.000000 ns',
}
